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E2U0063-18-82
Semiconductor MSM7582B
Semiconductor p/4 Shift QPSK MODEM
This version: MSM7582B Aug. 1998
GENERAL DESCRIPTION
The MSM7582B are CMOS ICs for the p/4 shift QPSK modem developed for the digital cordless telephone systems. The devices are designed for Personal and Cell station applications.
FEATURES
* Single Power Supply (VDD: 2.7 V to 3.6 V) (Modulator Block) * Built-in Root Nyquist Filter for Baseband Limiting (50% Roll-off) * Ramp Bit for Burst Signal Rise-up: 2.0 symbols * Ramp Bit for Burst Signal Fall-down: 2.0 symbols * Built-in D/A converters for Analog Output of Quadrature Signal I/Q Components and Power Envelope Output I2 + Q2 * Differential I/Q Analog output format * I/Q Output DC Offset / Gain Adjustable (Demodulator Block) * Full Digital System, p/4 shift QPSK Demodulation * Input IF signal Frequency Selectable: 1.2/10.7/10.75/10.8 MHz * Built-in Clock Recovery: 4 Circuits useful for Cell station (Common) * Various Power-down Modes: Tramsmit/Receive Independant * Built-in Precise Analog Voltage Reference * MCU Serial Interface for Mode setting and Built-in Test circuit * Test Modes: Eye pattern / AFC Compensating Signal / Phase Detection Signal, possible to monitor * Transmission Speed: 384 kbps * Low Power consumption Operating mode : 15 mA Typ. / Modulator (VDD = 3.0 V) : 9 mA Typ. / Demodulator (VDD = 3.0 V) Whole system Power-down mode: 0.01 mA Typ. (VDD = 3.0 V) * Package: 32-pin plastic TSOP (TSOPI32-P-814-0.50-1K)(Product name : MSM7582BTS-K)
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Semiconductor
MSM7582B
BLOCK DIAGRAM
SL4 SL3 SL2 SL1
PDN0 PDN1 PDN2
To monitor output of each block To modem ENV
V DD DGND AGND RXD
IFIN MCK IFCK
Phase Detector S E L
IFSEL1 (From CR) IFSEL0 (From CR)
Delay Detector
AFC
Decision RXC
SL1 SL2
S DPLL E L
To each block
X2 X1 DEN EXCK DIN DOUT Control Register
To each block
D E C
SL3 SL4
PS/CS (From CR)
AFC RPR RCW SLS1 SLS2 TXD TXW TXCI
I+ I- Q+ Q- ENV SG
+1 -1
DC offset adjustment
LPF
D/A
I output gain adjustment
Root Nyquist LPF
3.84MHz To D/A
S/P MAPPING PLL
+1 -1
DC offset adjustment
LPF
D/A
Q output gain adjustment LPF D/A
+1
S E L
S E L
To monitor output of each block
1/10 384kHz TXCSEL (From CR)
TXCO
VREF
To internal SG TEST1, TEST0 (From CR)
2/23
Semiconductor
MSM7582B
PIN CONFIGURATION (TOP VIEW)
AGND SG I+ I- Q+ Q- ENV PDN0 PDN1 PDN2 VDD SLS1 SLS2 RCW AFC RPR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DGND IFIN TXCI TXCO TXD TXW DEN EXCK DIN DOUT MCK RXD RXC IFCK X2 X1
32-Pin Plastic TSOP
3/23
Semiconductor
MSM7582B
PIN AND FUNCTIONAL DESCRIPTIONS
TXD Transmit data input for 384 kbps. TXCI Transmit clock input. When the control register CR0 - B6 is "0", a 384 kHz clock pulse synchronous with TXD should be input to this pin. This clock pulse should be continuous because these devices use APLL to generate the internal clock pulse. When CR0 - B6 is "1", a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz clock pulse is applied, TXCO outputs a 384 kHz clock pulse, which is generated by dividing the 3.84 MHz to TXCI by 10. The transmit data, synchronous 384 kHz clock pulse, should be input to the TXD. In this case the devices do not use APLL, and the 3.84 MHz clock pulse need not be continuous. (Refer to Fig. 1.) TXCO Transmit clock output. When CR0 - B6 is "0", TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring purposes. When CR0 - B6 is "1", this pin outputs a 384 kHz clock pulse generated by dividing the TXCI input by 10. (Refer to Fig. 1.) When CR0 - B6 = "0" and CR5 - B7 = "1", this pin outputs the burst timing position. TXW Transmit data window input. The transmit timing signal for the burst data is input to the device pin. If TXW is "1", the modulation data is output. (Refer to Fig. 1.)
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Semiconductor
MSM7582B
(1) CR0 - B6 = "0"
TXD TXCI (384 kHz) TXW TXCO (384 kHz) I, Q
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Delay of 6.25 symbols
(2) CR0 - B6 = "1"
TXD TXCI (3.84 MHz) TXW TXCO (384 kHz) I, Q
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Delay of 6.25 symbols
I+, I-
Quadrature modulation signal I component differential analog outputs. Their output levels are 500 mVpp with 1.6 Vdc as the center value. The output pin load conditions are: R 10 kW, C 20 pF. The gain of these pins can be adjusted using the control register CR1 - B7 to B4, and the offset voltage at the I- pin can be adjusted using CR3 - B7 to B3. Q+, Q- Quadrature modulation signal Q component differential analog outputs. Their output levels are 500 mVPP with 1.6 Vdc as the center value. The output pin load conditions are: R 10 kW, C 20 pF. The gain of these pins can be adjusted using the control register CR1 - B3 to B0, and the offset voltage at the Q- pin can be adjusted by using CR4 - B7 to B3.
, ,
Dn-1 Dn
MSM7582B
Ramp rise-up 2 symbols
Ramp fall-down 2 symbols
Delay of 6.25 symbols
Dn-1 Dn
Ramp rise-up 2 symbols
Ramp fall-down 2 symbols
Delay of 6.25 symbols
Figure 1 Transmit Timing Diagram
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Semiconductor ENV
MSM7582B
Quadrature modulation signal envelope ( I2 + Q2 )output. Its output level is 500 mVPP with 1.6 Vdc as a center value. The output pin load conditions are : R 10 kW, C 20 pF. The gain of this output can be adjusted using the control register CR2 - B7 to B4. This pin is also used to monitor eye pattern, AFC Compensating signal, and phase defection of the demodulator block during the test mode. Refer to the description of the control register for details. SG Internal reference voltage output. The output voltage is about 2.0 V. A bypass capacitor should be connected between this pin and the AGND pin. The external SG voltage, if necessary should be used via a buffer. PDN0, PDN1, PDN2 Inputs for power-down control. PDN0 controls the standby / communication modes, PDN1 controls the modulator, and PDN2 controls the demodulator. Refer to Table 1 for details. The control register should be reset by input of a signal with width of 200 ns or more. Table-1 Power Down Control
PDN0 PDN2 PDN1 0 Standby Mode 0 0 0/1 0 1 1 0 0 Function All power-down. The control register is reset. All power-down. The control register is not reset. Modulator power is off (VREF and PLL power are also off). Demodulator power is on. Modulator power is off (VREF and PLL power is on). 1 0 0 I and Q outputs are in a high-impedance state. Only demodulator clock recovery block power is on. 1 Communication Mode 1 1 0 0 1 Modulator power is on Only demodulator clock recovery block power is on. Modulator power is off (VREF and PLL power is on). I and Q outputs are in a high-impedance state. Demodulator power is on. 1 1 1 Modulator power is on Demodulator power is on. Mode G Mode F Mode E Mode D Mode Mode A Mode B Mode C
VDD +3 V power supply voltage. AGND Analog signal ground. DGND Digital signal ground. AGND and DGND pins should be connected as close as possible on the PCB. 6/23
Semiconductor MCK Master clock input. The clock frequency is 19.2 MHz. IFIN
MSM7582B
Modulated signal input for the demodulator block. Select the IF frequency from 1.2 MHz, 10.7 MHz, 10.75 MHz, and 10.8 MHz, based on CR0 - B4 and B3. IFCK Clock signal input for demodulator block IF frequencies (10.7 MHz or 10.75 MHz). If the IF frequency is 10.7 MHz, 19.0222 MHz should be supplied. When it is 10.75 MHz, 19.1111 MHz should be supplied. When the IF frequency is 1.2 MHz or 10.8 MHz, set this pin to "0" or "1". (Refer to Fig. 2.) X1, X2 Crystal oscillator connection pins. When supplying a 19.0222 MHz or 19.1111 MHz clock to IFCK, use these pins (Refer to Fig. 2.)
When IFIN = 10.7 MHz or 10.75 MHz When IFIN = 1.2 MHz or 10.8 MHz
MSM7582B X1 X2 IFCK X1
MSM7582B X2 IFCK
19.0222 MHz or 19.1111 MHz
Figure 2 How to Use IFCK, X1, and X2 RXD, RXC Receive data and clock output. When power is turned on, the outputs of circuits selected by SLS1 and SLS2 appear at these pins. (Refer to Fig. 3)
RXD1 RXC SLS2 SLS1
The recovery data and clock pulse are selected asynchronously using the SLS signals.
Figure 3 RXD and RXC Timing Diagram
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Semiconductor SLS2, SLS1
MSM7582B
Receiver slot select signal inputs. The devices have four sets of clock recovery circuit to each channel and four AFC information storage registers. One these circuits is selected from a combination of the signals at these pins. (SLS2, SLS1) = (0, 0): Slot 1, (0, 1): Slot 2 (1, 0): Slot 3, (1, 1): Slot 4 RPR High-speed phase clock control signal input for the clock recovery circuit. If this pin is "1", the clock recovery circuit starts in the high-speed phase clock mode. When the phase difference is less than a defined value, the circuit shifts to the low-speed phase clock mode automatically. When this pin is "0", the circuit is always in the low-speed phase clock mode. AFC AFC operation range specification signal input. As shown in Fig. 4, the AFC information is reset when both AFC and RPR are set to "1". AFC operation starts after a fixed number of clock cycles and after the AFC information is reset. If RPR is set to "1", an average number of times that AFC turns on is low. If RPR is "0", AFC is high. If AFC is "0", frequency error is not calculated, but the frequency is corrected using an error that is held. RCW Clock recovery circuit operation ON/OFF control signal input. If RCW pin is "0", DPLL does not make any phase corrections.
(CASE1) AFC RPR
AFC information is reset. Average number of times AFC is low. Average number of times AFC is high. AFC information is maintained.
(CASE2) AFC RPR
"0" The clock recovery circuit starts with the previous AFC information. Average number of times AFC is high. AFC information is maintained.
Figure 4 AFC Control Timing Diagram
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Semiconductor
MSM7582B
DEN , EXCK, DIN, DOUT
Serial control ports for the microprocessor interface. The MSM7582 and MSM7582B contain a 6-byte control register. An external CPU uses these pins to read data from and write data to the control register. DEN is an enable signal input pin. EXCK is a data shift clock pulse input pin. DIN is an address and data input pin. DOUT is a data output pin. Figure 5 shows an input/output timing diagram.
, ,
DEN EXCK DIN W A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 DOUT High Impedance (a) Data Write Timing Diagram DEN EXCK DIN R A2 A1 A0 DOUT High Impedance B7 B6 B5 B4 B3 B2 B1 B0 (b) Data Read Timing Diagram
Figure 5 MCU Interface Input/Output Timing Diagram
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Semiconductor
MSM7582B
The register map is shown below Table-2 Control Register Map
Register CR0 CR1 CR2 CR3 CR4 CR5 Address A2 0 0 0 0 1 1 A1 0 0 1 1 0 0 A0 0 1 0 1 0 1 B7 PS/CS Ich GAIN3 ENV GAIN3 Ich Offset4 Qch Offset4 BSTO ENBL B6 TXCSEL Ich GAIN2 ENV GAIN2 Ich Offset3 Qch Offset3 ICT6 B5 MODOFF Ich GAIN1 ENV GAIN1 Ich Offset2 Qch Offset2 ICT5 B4 IFSEL1 Ich GAIN0 ENV GAIN0 Ich Offset1 Qch Offset1 ICT4 Data B3 IFSEL0 Qch GAIN3 -- Ich Offset0 Qch Offset0 LOCAL INV1 B2 ENVSEL Qch GAIN2 -- -- -- LOCAL INV0 B1 TEST1 Qch GAIN1 -- -- -- CLK SEL1 B0 TEST0 Qch GAIN0 ICT0* -- -- CLK SEL0 R/W R/W R/W R/W R/W R/W R/W
R/W : Read/Write enable * Read-only register
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Semiconductor
MSM7582B
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Digital Input Voltage Storage Temperature
Symbol
Condtion -- -- --
Rating 0 to 5 -0.3 to VDD +0.3 -55 to +150
Unit V V C
VDD VDIN TSTG
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Input High Voltage Input Low Voltage Master Clock Frequency Modulator Input Frequency Demodulator Input Frequency Clock Duty Cycle IF Input Duty Cycle
Symbol
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Min. 2.7 -25
0.45 VDD
Condtion -- -- All digital input pins All digital input pins MCK TXCI (when CR0 - B6 = "0") TXCI (when CR0 - B6 = "1")
Typ. -- +25 -- -- 19.2 384 3.84 19.0222 19.1111 50 50
Max. 3.6 +70 VDD
0.16 VDD
Unit V C V V MHz kHz MHz MHz MHz % %
VDD Ta VIH VIL fMCK fTXC1 fTXC2
0 -- -- -- -50 ppm 40 45
-- -- -- +50 ppm +50 ppm 60 55
fIFCK1 IFCK (when IFIN = 10.7 MHz) DCCK MCK, IFCK, TXCI DCIF IFCK
fIFCK2 IFCK (when IFIN = 10.75 MHz) -50 ppm
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
Symbol
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Condition Mode A, Mode B (when VDD = 3.0 V) Mode C (when VDD = 3.0 V) Mode D (when VDD = 3.0 V) Mode E (when VDD = 3.0 V) Mode F (when VDD = 3.0 V) Mode G (when VDD = 3.0 V) IOH = 0.4 mA IOL = -1.2 mA -- -- Min. -- -- -- -- -- --
0.5 VDD
Typ. 0.02 5.5 5.5 11.5 9.5 14.0 -- -- -- --
Max. 0.05 11.0 11.0 23.0 19.0 28.0 VDD 0.4 10 10
Unit mA mA mA mA mA mA V V mA mA
IDD1 IDD2 Power Supply Current IDD3 IDD4 IDD5 IDD6 Output High Voltage Output Low Voltage Input Leakage Current VOH VOL IIH IIL
0.0 -- --
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Semiconductor Analog Interface Characteristics
Parameter Output Resistance Load Output Capacitance Load
Symbol
MSM7582B
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Condtion I+, I-, Q+, Q-, ENV I+, I-, Q+, Q-, ENV I+, I-, Q+, Q- (TXW = 0) I+ (CR0 - B5 = 1) when not modulated Q+ (CR0 - B5 = 1) when not modulated ENV (TXW = 0)
ENV (TXW = 1, CR0 - B2 = 0, TXD = 0) ENV (TXW = 1, CR0 - B2 = 1, TXD = 0)
Min. 10 -- 1.55 -- -- -- -- -- 340 -20 -- -- 60 65 -- 0.4 -- -- -- -- --
Typ. -- -- 1.6 1.77 1.67 1.35 1.72 1.63 360 -- 45 4 -- -- 1.0 -- 20 5 2.0 2 400
Max. -- 20 1.65 -- -- -- -- -- 380 +20 -- -- -- -- 3.0 VDD -- -- -- -- --
Unit kW pF V V V V V V mVPP mV mV % dB dB % rms VPP kW pF V kW ms
RLIQ CLIQ VDC1 VDC2 VDC3 VDC4 VDC5 VDC6
Output DC Voltage Level
Output AC Voltage Level Offset Voltage Difference
Output DC Voltage Adjustment Level Range Output AC Voltage Adjustment Level Range
VAC VOFF DCVL ACVL
I+, I-, Q+, Q- (TXD = 0) Difference among I+, I-, Q+, and Q- -- --
Out-of-band Spectrum Modulation Accuracy Demodulator IF Input Level IFIN Input Impedance SG Output Voltage SG Output Impedance SG Warm-up Time Modulator D/A Conversion sampling Frequency Modulator D/A Conversion offset Frequency
P600 600 kHz detuning (*) P900 900 kHz detuning (*) EVM IFV RIF CIF VSG RSG TSG -- IFIN input level -- -- -- -- SGAGND 0.1mF (Rise time to 90 % of max. level) FSDA FCDA -- --
-- --
1.92 380
-- --
MHz kHz
* Power attenuation at 600 kHz or 900 kHz 96 kHz as referred to two times of the power in frequency band of 0 to 96 kHz
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Semiconductor Digital Interface Characteristics
Parameter
Symbol
MSM7582B
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Condtion Other Min. -200 0 C load = 50 pF Fig. 6 0 0 0 0 Fig. 7 10 10 50 50 50 50 100 C load = 50 pF Fig. 8 50 50 0 50 50 0 -- EXCK -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 200 200 200 200 -- -- -- -- -- -- -- -- -- 100 -- -- 50 10 ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns MHz Typ. -- -- Max. +200 200 Unit ns ns
tSX tDS Transmitter Digital Input/Output Setting Time tDH tXD1 tXD2 tXD3 tXD4 tRD1 Receiver Digital Input/Output Setting Time tRD2 tRS1 to C load = 50 pF tRS4 tRW tM1 tM2 tM3 tM4 Serial Port Digital Input/Output Setting Time tM5 tM6 tM7 tM8 tM9 tM10 tM11 EXCK Clock Frequency fEXCK
13/23
Semiconductor
MSM7582B
TIMING DIAGRAM
Transmit Data Input Timing
TXCI [TXCO*] (384 kHz) TXW TXD 1 tSX
Transmit Clock (TXCO) Output Timing (when CR0 - B6 = 1)
TXCI (3.84 MHz) TXCO (384 kHz) 1 2 3 4 5 6 7
Transmit Burst Position Output (TXCO) Timing (when CR0 - B6 = 0 and CR5 - B7 = 1)
M7582 TXCI (384 kHz) TXW tXD3 TXCO M7582B TXCI (384 kHz) TXW tXD3 TXCO 1 2 8 9 N
N+1 N+17 N+18

2 3 N-2 N-1 N N+1 tSX tDS tDH 1 2 3 N-2 N-1 N * [ ]: When CR0 - B6 = "1", TXCO is indicated. 8 9 10 tXD1 tXD2 tXD1 1 2 8 9 N
N+1 N+17 N+18 N+19
tXD4
N+19
tXD4
Figure 6 Transmit (Modulator) Digital Input/Output Timing
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Semiconductor
MSM7582B
SLS1 SLS2 RCW
tRS1 tRS2 tRS3 tRS4
AFC RPR RXC tRD1 RXD
tRW
tRD2
Figure 7 Receiver (Demodulator) Digital Input/Output Timing
DEN tM2 EXCK tM1 1 tM3 2 3 tM6 4 tM7 tM5 5 6 11 12 tM4 tM10
tM4 W/R A2
DIN
A1
A0
B7 tM8
B1
B0 tM11
DOUT
B7
B1
B0
Figure 8 Serial Control Port Interface
15/23
Semiconductor
MSM7582B
FUNCTIONAL DESCRIPTION
Control Registers (1) CR0 (basic operation mode setting)
B7 CR0 Initial value (*) PS/CS 0 B6 TXC SEL 0 B5 MOD OFF 0 B4 IFSEL 1 0 B3 IFSEL 0 0 B2 ENV SEL 0 B1 TEST 1 0 B0 TEST 0 0
* the initial value is set when a reset signal is supplied by a PDN. B7: PS/CS selection 1/CS (4 Clock recovery DPLLs are on.) 0/PS (2 Clock recovery DPLLs are on.) B6: Transmit timing clock selection 0/TXCI input: 384 kHz. TXCO output: 384 kHz output from APLL. Transmit data TXD is input in synchronization with the rising edge of TXCI (APLL is on.) 1/TXCI input: 3.84 MHz. TXCO output: 384 kHz (one-tenth of the TXCI frequency). Transmit data TXD is input in synchronization with the rising edge of TXCO (APLL is off.) B5: Modulation on/off control 1/modulation OFF (with phase fixed) 0/modulation ON. B4, B3: Receiver input IF frequency selection (0, 0), (0, 1): 1.2 MHz (1, 0): 10.8 MHz (1, 1): 10.7 MHz/10.75 MHz B2: Transmit envelope (I2 + Q2 or I2 + Q2 )output selection 1/I2 + Q2 output 0/ I2 + Q2 output B1, B0: Test mode selection bits. Each monitor output is output to the transmit ENV pin. (0, 0): Transmit envelope (I2 + Q2 or I2 + Q2 ) output (0, 1): receiver phase detection signal output (1, 0): receiver delay detection signal output (1, 1): receiver AFC information output
16/23
Semiconductor
MSM7582B
(2) CR1 (I, Q gain adjustment)
B7 CR1 Initial value Ich GAIN3 0 B6 Ich GAIN2 0 B5 Ich GAIN1 0 B4 Ich GAIN0 0 B3 Qch GAIN3 0 B2 Qch GAIN2 0 B1 Qch GAIN1 0 B0 Qch GAIN0 0
B7 to B4: I+/I- output gain setting, in 3 mV steps (Refer to Table-3.) B3 to B0: Q+/Q- output gain setting, in 3 mV steps (Refer to Table-3.) (3) CR2 (ENV gain adjustment)
B7 CR2 Initial value ENV GAIN3 0 B6 ENV GAIN2 0 B5 ENV GAIN1 0 B4 ENV GAIN0 0 B3 -- 0 B2 -- 0 B1 -- 0 B0 ICT0 1
B7 to B4: ENV output gain adjustment (Refer to Table-3.) B3 to B1: Not used B0 : Device test control bit. Table-3 I, Q, and ENV Output Gain Values
CR1-B7 CR1-B3 CR2-B7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 -B6 -B5 -B4 -B2 -B1 -B0 -B6 -B5 -B4 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Amplitude 1.042 Reference value 1.036 1.030 1.024 1.018 1.012 1.006 1.000 (Reference value) 0.994 0.988 0.982 0.976 0.970 0.964 0.958 0.952 Description
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Semiconductor
MSM7582B
(4) CR3 (I- output offset voltage adjustment)
B7 CR3 Initial value Ich Offset4 0 B6 Ich Offset3 0 B5 Ich Offset2 0 B4 Ich Offset1 0 B3 Ich Offset0 0 B2 -- 0 B1 -- 0 B0 -- 0
B7 to B3: I- output pin offset voltage adjustment (Refer to Table-4.) B2 to B0: Not used (5) CR4 (Q- output offset voltage adjustment)
B7 CR4 Initial value Qch Offset4 0 B6 Qch Offset3 0 B5 Qch Offset2 0 B4 Qch Offset1 0 B3 Qch Offset0 0 B2 -- 0 B1 -- 0 B0 -- 0
B7 to B4: Q- output pin offset voltage adjustment (Refer to Table-4.) B3 to B1: Not used Table-4 I and Q Channel Offset Adjustment Values
CR3-B7 CR4-B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B6 B6 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B5 B5 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B4 B4 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B3 B3 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Description Offset +45 mV +42 mV +39 mV +36 mV +33 mV +30 mV +27 mV +24 mV +21 mV +18 mV +15 mV +12 mV +9 mV +6 mV +3 mV 0 mV CR3-B7 CR4-B7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B6 B6 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B5 B5 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B4 B4 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B3 B3 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Description Offset -3 mV -6 mV -9 mV -12 mV -15 mV -18 mV -21 mV -24 mV -27 mV -30 mV -33 mV -36 mV -39 mV -42 mV -45 mV -48 mV
18/23
Semiconductor (6) CR5
B7 CR5 Initial value BSTO ENBL 0 B6 ICT6 0 B5 ICT5 0 B4 ICT4 0 B3 LOCAL INV1 0 B2 LOCAL INV0 0 B1 CLK SEL1 0
MSM7582B
B0 CLK SEL0 0
B7: Modulator burst window output enable bit. 1/The timing of the I and Q baseband modulation output burst is output at the TXCO pin. 0/The 384 kHz transmit timing clock pulse is output at the TXCO pin. B6 to B4: ICT6 to ICT4. Device test control bits. B3, B2: Local inverting mode setting bits. (1, 1) = local inverting mode (0, 0) = normal mode B1: Clock pulse shaping mode selection bit. 1/Clock pulse shaping mode (Refer to Fig 9.) 0/Oscillator circuit mode B0: Power-on control bit for X1, X2 pins, when the clock pulse shaping mode. 1/ Always power-on 0/ Power-down in the whole device power-down state when Power on otherwise. Note: CR5 - B6 to B4 are used to test the device. They should be set to "0" during normal operation.
MSM7582B TS-K X1 TCXO 19.2 MHz About Pulse shape To other input 0.7 to 1.0 VPP within about 3 VPP of 19.2 MHz X2 MCK
Figure 9 Example of Application Circuit when the Clock Pulse Shaping Mode is Generated by CR5-B1
19/23
Semiconductor State Transition Time
Mode A* PDN1 = 1 Note: The transition time is 1 ms or less unless otherwise stated Mode B Standby mode (PDN0 = 0) Communication mode (PDN0 = 1) 40 ms Mode E PDN1 = 1 PDN2 = 0 5 ms Mode G PDN1 = 1 PDN2 = 1 5 ms PDN1 = 0 PDN2 = 0 5 ms Mode D PDN1 = 0 PDN2 = 0 40 ms Mode F
MSM7582B
1 ms Mode C PDN1 = 0 PDN2 = 1
PDN1 = 0 PDN2 = 1
* Note that this state clears the register.
Figure 10 Power-Down State Transition Time
20/23
Semiconductor
MSM7582B
APPLICATION CIRCUIT
VDD
C1 +
To orthogonal modulator
C2
C3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AGND SG I+ I- Q+ Q- ENV PDN0 PDN1 PDN2 VDD SLS1 SLS2 RCW AFC RPR
Modulator I component output Modulator Q component output
MSM7582BTS-K
Power-down control signal
DGND IFIN TXCI TXCO TXD TXW DEN EXCK DIN DOUT MCK RXD RXC IFCK X2 X1
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
C4
Demodulator IF input Modulator 384 kHz input Modulator input data Modulator data window
19.2 MHz input Receive data output Receive clock output
Demodulator control signal C1 = 10 mF C2 = C3 = 0.1 mF C4 = 1000 pF
Control register control signal
Figure 11 Example of Circuit Configuration
21/23
Semiconductor Demodulator Control Timing Diagram (Example)
Democulator unit Modulator input data
Timing for CS PDN2 SLS2 SLS1 AFC Slot 1
R1
MSM7582B
RXD RXC
Timing for PS PDN2 SLS2 SLS1 AFC
RXD RXC
(1) Control channel / synchronous burst (SS + PR = 64 bits)
RXD AFC
RPR
RCW
(2) When synchronization is not established (for PS only)
AFC
RPR
RCW
(3) Communication channel (SS + PR = 8 bits)
RXD AFC
RPR
,
Slot 2
R2
Slot 3
R3
Slot 4
R4
G
G
G
G
G
"0" "0"
"0" "1"
"1" "0"
"1" "1"
R1
R2
R3
R4
"0" "0"
R1
240 bits 625 ms
64 bits
G G G G G G G G R R R R SS SS PR PR
PR UW
CR CR G G G G G G G G
56 bits
For PS, the window is initially open to wait for the control signal from CS. RPR is closed after UW is detected. 8 bits
G G G G G G G G R R R R SS SS PR PR
PR UW
CR CR G G G G G G G G
"0"
RCW Less than 30 bits G: R: SS : PR : UW : CR : Guard bit Ramp bit Start symbol bit Preamble bit Unique word bit CRC bit
Note: AFC and RCW may be controlled at the same timing.
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Semiconductor
MSM7582B
PACKAGE DIMENSIONS
(Unit : mm)
TSOPI32-P-814-0.50-1K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.27 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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